Difference between revisions of "Instruction Set/shiftluw"
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| − | bitwise shift | + | Unsigned bitwise left shift. Widening. |
| + | The bit count by which to shift is an unsigned number. | ||
| + | The higher order bits get zero extended in the widening. | ||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">shiftluw</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bits</span></i>) → [[Domains#u|u]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">shiftluw</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bits</span></i>) → [[Domains#u|u]] r<sub>0</sub></code> | ||
Revision as of 10:32, 11 January 2015
realizing exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes
native on: all
Unsigned bitwise left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get zero extended in the widening.
shiftluw(u x, bit bits) → u r0
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 1 |
| Copper | E0 | 1 |
| Silver | E0 E1 | 1 |
| Gold | E0 E1 | 1 |
| Decimal8 | E0 E1 | 1 |
| Decimal16 | E0 E1 | 1 |
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 1 |
| Copper | E0 | 1 |
| Silver | E0 E1 | 1 |
| Gold | E0 E1 | 1 |
| Decimal8 | E0 E1 | 1 |
| Decimal16 | E0 E1 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
