Difference between revisions of "Instruction Set/f2udxfz"
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Revision as of 01:32, 3 January 2015
realizing exu stream exu block compute phase operation in the decimal floating point value domain using excepting overflow behavior that produces condition codes and rounds to nearest, ties away from zero
Inexactly convert a decimal floating point value to a unsigned integer, rounding away from zero and producing NaRs on overflow.
operands: like Addd [dd:d]
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
