Difference between revisions of "Instruction Set/narrowde"

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narrow scalar to half width
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Half the width of a decimal float value. Rounding to nearest even.
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Can produce the [http://en.wikipedia.org/wiki/IEEE_floating_point IEEE 754] 32bit decimal float interchange format.
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This is not a [[Speculable]] operation. The reason for this is the impossibility to fit all of the [[NaR]] payload into values smaller than 32bit.
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Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so.
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If narrowing should prove a big bottleneck this can be revisited.
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<code style="font-size:130%"><b style="color:#050">narrowde</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">v</span>) &#8594; [[Domains#d|d]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">narrowde</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">v</span>) &#8594; [[Domains#d|d]] r<sub>0</sub></code>

Revision as of 00:05, 3 January 2015

realizing  exu stream  exu block  compute phase   operation   in the decimal floating point value domain   and rounds to nearest, ties toward even adjacent value

native on: Decimal8 Decimal16

Half the width of a decimal float value. Rounding to nearest even.

Can produce the IEEE 754 32bit decimal float interchange format.

This is not a Speculable operation. The reason for this is the impossibility to fit all of the NaR payload into values smaller than 32bit. Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. If narrowing should prove a big bottleneck this can be revisited.


narrowde(d v) → d r0

operands: like Narrowd [dd:½d]


Core In Slots Latencies
Decimal8 E0 E1 d:w=4 q:d=5
Decimal16 E0 E1 d:w=4 q:d=5

narrowde(d v1, d v2) → d r0

operands: like Narrowvd [DD:½D]


Core In Slots Latencies
Decimal8 E0 E1 dv,dv:wv=4 qv,qv:dv=5
Decimal16 E0 E1 dv,dv:wv=4 qv,qv:dv=5


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