Difference between revisions of "Instruction Set/nor"
From Mill Computing Wiki
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− | + | Bitwise nor. | |
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+ | <b>related operations:</b> [[Instruction_Set/andl|andl]], [[Instruction_Set/orl|orl]], [[Instruction_Set/flip|flip]], [[Instruction_Set/nand|nand]], [[Instruction_Set/xorl|xorl]], [[Instruction_Set/nxor|nxor]], [[Instruction_Set/imp|imp]], [[Instruction_Set/nimp|nimp]] | ||
+ | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">nor</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#op|op]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">nor</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#op|op]] r<sub>0</sub></code> |
Revision as of 18:53, 20 December 2014
realizing exu stream exu block compute phase operation in the logical value domain
aliases: nors noru
native on: all
Bitwise nor.
related operations: andl, orl, flip, nand, xorl, nxor, imp, nimp
operands: like Identity [xx:x]
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | 1 |
Copper | E0 E1 | 1 |
Silver | E0 E1 E2 E3 | 1 |
Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 1 |
Decimal8 | E0 E1 E2 E3 | 1 |
Decimal16 | E0 E1 E2 E3 | 1 |
operands: like Identity [xx:x]
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | 1 |
Copper | E0 E1 | 1 |
Silver | E0 E1 E2 E3 | 1 |
Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 1 |
Decimal8 | E0 E1 E2 E3 | 1 |
Decimal16 | E0 E1 E2 E3 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable