Difference between revisions of "Instruction Set/mulsx"
From Mill Computing Wiki
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| − | + | Signed Integer multiply. Excepting. | |
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<code style="font-size:130%"><b style="color:#050">mulsx</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#s|s]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">mulsx</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#s|s]] r<sub>0</sub></code> | ||
Revision as of 18:52, 20 December 2014
realizing exu stream exu block compute phase operation in the signed integer value domain using excepting overflow behavior that produces condition codes
aliases: mulsxv
native on: all
Signed Integer multiply. Excepting.
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Copper | E0 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Silver | E0 E1 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Gold | E0 E1 E2 E3 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Decimal8 | E0 E1 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Decimal16 | E0 E1 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
