Difference between revisions of "Instruction Set/rdivu"
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| − | reciprocal | + | Unsigned integer reciprocal dividion. Helper operation for software division implementation. |
| + | |||
| + | This operation creates a seed value for Newton-Rapheson, or other, iterative division. | ||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">rdivu</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#u|u]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">rdivu</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#u|u]] r<sub>0</sub></code> | ||
Revision as of 00:06, 3 January 2015
realizing exu stream exu block compute phase operation in the unsigned integer value domain
native on: all
Unsigned integer reciprocal dividion. Helper operation for software division implementation.
This operation creates a seed value for Newton-Rapheson, or other, iterative division.
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 |
| Copper | E0 E1 | b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 |
| Silver | E0 E1 E2 E3 | b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 |
| Decimal8 | E0 E1 E2 E3 | b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 |
| Decimal16 | E0 E1 E2 E3 | b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 |
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