Difference between revisions of "Instruction Set/adddz"
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{{DISPLAYTITLE:adddz}} | {{DISPLAYTITLE:adddz}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the decimal floating point value domain]] [[Condition Code|that produces condition codes]]<br /> | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the decimal floating point value domain]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward zero]]<br /> |
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br /> | '''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br /> | ||
</div> | </div> | ||
Revision as of 18:52, 20 December 2014
realizing exu stream exu block compute phase operation in the decimal floating point value domain that produces condition codes and rounds toward zero
Decimal floating point add in current rounding towards zero.
operands: like Addd [dd:d]
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5 |
| Decimal16 | E0 E1 | d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
