Difference between revisions of "Instruction Set/shiftluwv"
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m (Protected "Instruction Set/shiftluwv": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite))) | |
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Revision as of 01:32, 3 January 2015
realizing exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes
native on: all
bitwise shift
shiftluwv(u x, bit bits) → u r0, u r1
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 | 2 2 |
| Silver | E0 E1 | 2 2 |
| Gold | E0 E1 | 2 2 |
| Decimal8 | E0 E1 | 2 2 |
| Decimal16 | E0 E1 | 2 2 |
shiftluwv(u x, n bits) → u r0, u r1
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 | 2 2 |
| Silver | E0 E1 | 2 2 |
| Gold | E0 E1 | 2 2 |
| Decimal8 | E0 E1 | 2 2 |
| Decimal16 | E0 E1 | 2 2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
