Difference between revisions of "Instruction Set/countrfl"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#245|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#countrfl|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#245|Copper]] || E0 || 1
+
| [[Cores/Copper/Encoding#countrfl|Copper]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#245|Silver]] || E0 || 1
+
| [[Cores/Silver/Encoding#countrfl|Silver]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#245|Gold]] || E0 || 1
+
| [[Cores/Gold/Encoding#countrfl|Gold]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#245|Decimal8]] || E0 || 1
+
| [[Cores/Decimal8/Encoding#countrfl|Decimal8]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#245|Decimal16]] || E0 || 1
+
| [[Cores/Decimal16/Encoding#countrfl|Decimal16]] || E0 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

Count the zero bits from the right.

related operations: countlfl, countltr, countrtr

countrfl(op x) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 1
Copper E0 1
Silver E0 1
Gold E0 1
Decimal8 E0 1
Decimal16 E0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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