Difference between revisions of "Instruction Set/addswv"

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Line 16:Line 16:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#198|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#addswv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#198|Copper]] || E0 E1 || 2 2
+
| [[Cores/Copper/Encoding#addswv|Copper]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#198|Silver]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Silver/Encoding#addswv|Silver]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#198|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
+
| [[Cores/Gold/Encoding#addswv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#198|Decimal8]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal8/Encoding#addswv|Decimal8]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#198|Decimal16]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal16/Encoding#addswv|Decimal16]] || E0 E1 E2 E3 || 2 2
 
|}
 
|}
  
Line 38:Line 38:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#199|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#addswv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#199|Copper]] || E0 E1 || 2 2
+
| [[Cores/Copper/Encoding#addswv|Copper]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#199|Silver]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Silver/Encoding#addswv|Silver]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#199|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
+
| [[Cores/Gold/Encoding#addswv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#199|Decimal8]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal8/Encoding#addswv|Decimal8]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#199|Decimal16]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal16/Encoding#addswv|Decimal16]] || E0 E1 E2 E3 || 2 2
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Widening signed integer vector addition. If any of the result values in the vector overflows, the vector is widened as with widenuv.

addswv(s x, s y) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2

addswv(s x, imm y) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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