Difference between revisions of "Instruction Set/loadd"

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Line 15:Line 15:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#520|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#520|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 31:Line 31:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#531|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#531|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 47:Line 47:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#533|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#533|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 61:Line 61:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#525|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#525|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 75:Line 75:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#522|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#522|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 90:Line 90:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#526|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#526|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 105:Line 105:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#523|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#523|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 121:Line 121:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#524|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#524|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 137:Line 137:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#527|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#527|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 151:Line 151:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#530|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#530|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 165:Line 165:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#528|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#528|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 180:Line 180:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#521|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#521|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 195:Line 195:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#529|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#529|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 210:Line 210:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#532|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#532|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
  
Line 225:Line 225:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#534|Decimal8]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal8/Encoding#loadd|Decimal8]] || F0 F1 F2 F3 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#534|Decimal16]] || F0 F1 F2 F3 || 3
+
| [[Cores/Decimal16/Encoding#loadd|Decimal16]] || F0 F1 F2 F3 || 3
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  flow stream  flow block  compute phase   operation   in the decimal floating point value domain  

native on: Decimal8 Decimal16

load from memory

loadd(base b, off o, s i, scale s, width w) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(base b, off o, s i, scale s, width w, lit delay) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(base b, off o, s i, scale s, width w, tag tag) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(base b, off o, width w) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(base b, off o, width w, lit delay) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(base b, off o, width w, tag tag) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(p b, off o, s i, scale s, width w) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(p b, off o, s i, scale s, width w, lit delay) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(p b, off o, s i, scale s, width w, tag tag) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(p b, off o, width w) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(p b, off o, width w, lit delay) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(p b, off o, width w, tag tag) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(p b, width w, memAttr m) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(p b, width w, memAttr m, lit delay) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3

loadd(p b, width w, memAttr m, tag tag) → d r0

operands: like IdentityNoSIMD xx:x


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 3
Decimal16 F0 F1 F2 F3 3


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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