Difference between revisions of "Instruction Set/load"
Line 15: | Line 15: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 39: | Line 39: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 63: | Line 63: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 85: | Line 85: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 107: | Line 107: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 130: | Line 130: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 153: | Line 153: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 177: | Line 177: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 201: | Line 201: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 223: | Line 223: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 245: | Line 245: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 268: | Line 268: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 291: | Line 291: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 314: | Line 314: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
Line 337: | Line 337: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#load|Tin]] || F0 || 3 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#load|Copper]] || F0 F1 || 3 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#load|Silver]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#load|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 3 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#load|Decimal8]] || F0 F1 F2 F3 || 3 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#load|Decimal16]] || F0 F1 F2 F3 || 3 |
|} | |} | ||
+ | |||
+ | |||
+ | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] |
Revision as of 02:37, 16 December 2014
load from memory
load(base b, off o, s i, scale s, width w) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(base b, off o, s i, scale s, width w, lit delay) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(base b, off o, s i, scale s, width w, tag tag) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(base b, off o, width w) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(base b, off o, width w, lit delay) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(base b, off o, width w, tag tag) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(p b, off o, s i, scale s, width w) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(p b, off o, s i, scale s, width w, lit delay) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(p b, off o, s i, scale s, width w, tag tag) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(p b, off o, width w) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(p b, off o, width w, lit delay) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(p b, off o, width w, tag tag) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(p b, width w, memAttr m) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(p b, width w, memAttr m, lit delay) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
load(p b, width w, memAttr m, tag tag) → op r0
Core | In Slots | Latencies |
---|---|---|
Tin | F0 | 3 |
Copper | F0 F1 | 3 |
Silver | F0 F1 F2 F3 | 3 |
Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 3 |
Decimal8 | F0 F1 F2 F3 | 3 |
Decimal16 | F0 F1 F2 F3 | 3 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable