Difference between revisions of "Instruction Set/addsw"

From Mill Computing Wiki
Jump to: navigation, search
Line 16:Line 16:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#196|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Tin/Encoding#addsw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#196|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Copper/Encoding#addsw|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#196|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Silver/Encoding#addsw|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#196|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Gold/Encoding#addsw|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#196|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Decimal8/Encoding#addsw|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#196|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Decimal16/Encoding#addsw|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|}
 
|}
  
Line 38:Line 38:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#197|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Tin/Encoding#addsw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#197|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Copper/Encoding#addsw|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#197|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Silver/Encoding#addsw|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#197|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Gold/Encoding#addsw|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#197|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Decimal8/Encoding#addsw|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#197|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
+
| [[Cores/Decimal16/Encoding#addsw|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2  
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:36, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Widening signed integer addition. When a result value overflows, it is widened.

addsw(s x, s y) → s r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Copper E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Silver E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Gold E0 E1 E2 E3 E4 E5 E6 E7 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal8 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal16 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2

addsw(s x, imm y) → s r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Copper E0 E1 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Silver E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Gold E0 E1 E2 E3 E4 E5 E6 E7 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal8 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
Decimal16 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Retrieved from "http://millcomputing.com/w/index.php?title=Instruction_Set/addsw&oldid=1538"