Difference between revisions of "Instruction Set/adduwv"

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Line 16:Line 16:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#206|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#adduwv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#206|Copper]] || E0 E1 || 2 2
+
| [[Cores/Copper/Encoding#adduwv|Copper]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#206|Silver]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Silver/Encoding#adduwv|Silver]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#206|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
+
| [[Cores/Gold/Encoding#adduwv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#206|Decimal8]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal8/Encoding#adduwv|Decimal8]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#206|Decimal16]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal16/Encoding#adduwv|Decimal16]] || E0 E1 E2 E3 || 2 2
 
|}
 
|}
  
Line 38:Line 38:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#207|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#adduwv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#207|Copper]] || E0 E1 || 2 2
+
| [[Cores/Copper/Encoding#adduwv|Copper]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#207|Silver]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Silver/Encoding#adduwv|Silver]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#207|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
+
| [[Cores/Gold/Encoding#adduwv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#207|Decimal8]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal8/Encoding#adduwv|Decimal8]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#207|Decimal16]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal16/Encoding#adduwv|Decimal16]] || E0 E1 E2 E3 || 2 2
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:36, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Widening unsigned integer vector addition. If any of the result values in the vector overflows, the vector is widened as with widenuv.

adduwv(u x, u y) → u r0, u r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2

adduwv(u x, imm y) → u r0, u r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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