Difference between revisions of "Instruction Set/innerfln"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
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| [[Cores/Tin/Encoding#1009|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#innerfln|Tin]] || F0 || 1
 
|-
 
|-
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| [[Cores/Copper/Encoding#1009|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#innerfln|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1009|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#innerfln|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
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| [[Cores/Gold/Encoding#1009|Gold]] || F0 F1 F2 F3 || 1
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| [[Cores/Gold/Encoding#innerfln|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
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| [[Cores/Decimal8/Encoding#1009|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#innerfln|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1009|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#innerfln|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1010|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#innerfln|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1010|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#innerfln|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1010|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#innerfln|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1010|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#innerfln|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1010|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#innerfln|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1010|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#innerfln|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  flow stream  flow block  call phase   operation  

native on: all

enter a loop

innerfln(op q, lit n, p target, args args) → ops r0 ...rn

operands: like Inv :


encoding: innerfln(op q, lit n, p target, off argc, count args)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

innerfln(op q, lit n, lbl target, args args) → ops r0 ...rn

operands: like Inv :


encoding: innerfln(op q, lit n, off target, count argc) , innerfln(op q, lit n, off target, count argc, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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