Difference between revisions of "Instruction Set/innertrn"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1017|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#innertrn|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1017|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#innertrn|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1017|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#innertrn|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1017|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#innertrn|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1017|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#innertrn|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1017|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#innertrn|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
Line 48:Line 48:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1018|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#innertrn|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1018|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#innertrn|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1018|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#innertrn|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1018|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#innertrn|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1018|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#innertrn|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1018|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#innertrn|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  flow stream  flow block  call phase   operation  

native on: all

enter a loop

innertrn(op q, lit n, p target, args args) → ops r0 ...rn

operands: like Inv :


encoding: innertrn(op q, lit n, p target, off argc, count args)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

innertrn(op q, lit n, lbl target, args args) → ops r0 ...rn

operands: like Inv :


encoding: innertrn(op q, lit n, off target, count argc) , innertrn(op q, lit n, off target, count argc, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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