Difference between revisions of "Instruction Set/calltrn"

From Mill Computing Wiki
Jump to: navigation, search
Line 19:Line 19:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#954|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#calltrn|Tin]] || F0 || 1
 
|-
 
|-
| [[Cores/Copper/Encoding#954|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#calltrn|Copper]] || F0 F1 || 1
 
|-
 
|-
| [[Cores/Silver/Encoding#954|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#calltrn|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
| [[Cores/Gold/Encoding#954|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#calltrn|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
| [[Cores/Decimal8/Encoding#954|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#calltrn|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
| [[Cores/Decimal16/Encoding#954|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#calltrn|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
Line 48:Line 48:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#955|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#calltrn|Tin]] || F0 || 1
 
|-
 
|-
| [[Cores/Copper/Encoding#955|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#calltrn|Copper]] || F0 F1 || 1
 
|-
 
|-
| [[Cores/Silver/Encoding#955|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#calltrn|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
| [[Cores/Gold/Encoding#955|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#calltrn|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
| [[Cores/Decimal8/Encoding#955|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#calltrn|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
| [[Cores/Decimal16/Encoding#955|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#calltrn|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  flow stream  flow block  call phase   operation  

native on: all

function call


calltrn(op q, lit n, p target, args args) → ops r0 ...rn

operands: like Inv :


encoding: calltrn(op q, lit n, p target, off argc, count args)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

calltrn(op q, lit n, lbl target, args args) → ops r0 ...rn

operands: like Inv :


encoding: calltrn(op q, lit n, off target, count argc) , calltrn(op q, lit n, off target, count argc, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable