Difference between revisions of "Instruction Set/negswv"

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(Created page with "{{DISPLAYTITLE:negswv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu block...")
 
 
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{{DISPLAYTITLE:negswv}}
 
{{DISPLAYTITLE:negswv}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#678|Tin]] || E0 || 2 2
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| [[Cores/Tin/Encoding#negswv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#678|Copper]] || E0 E1 || 2 2
+
| [[Cores/Copper/Encoding#negswv|Copper]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#678|Silver]] || E0 E1 E2 E3 || 2 2
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| [[Cores/Silver/Encoding#negswv|Silver]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#678|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
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| [[Cores/Gold/Encoding#negswv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#678|Decimal8]] || E0 E1 E2 E3 || 2 2
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| [[Cores/Decimal8/Encoding#negswv|Decimal8]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#678|Decimal16]] || E0 E1 E2 E3 || 2 2
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| [[Cores/Decimal16/Encoding#negswv|Decimal16]] || E0 E1 E2 E3 || 2 2
 
|}
 
|}
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 +
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 09:33, 9 February 2015

speculable  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

negate

negswv(s x) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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