Difference between revisions of "Instruction Set/widendv"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:widendv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exu bloc...") | |||
| (3 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
{{DISPLAYTITLE:widendv}} | {{DISPLAYTITLE:widendv}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the decimal floating point value domain]] <br /> |
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br /> | '''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br /> | ||
</div> | </div> | ||
| − | widen to | + | Double the scalar width of the elements of a decimal float vector. |
| + | |||
| + | Decimal floats can be 4-16 byte wide. Although the 4 byte format is a pure interchange format and no floating arithmetic operations are available for them. | ||
| + | |||
| + | Vector widen operations always produce two result vectors to accomodate the widening of maximum size vectors. The first result vector then contains the widened values of the lower half of the operand, and the second result the upper. | ||
| + | |||
| + | |||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">widendv</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">v</span>) → [[Domains#d|d]] r<sub>0</sub>, [[Domains#d|d]] r<sub>1</sub></code> | <code style="font-size:130%"><b style="color:#050">widendv</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">v</span>) → [[Domains#d|d]] r<sub>0</sub>, [[Domains#d|d]] r<sub>1</sub></code> | ||
| Line 14: | Line 21: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#widendv|Decimal8]] || E0 E1 || 2 2 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#widendv|Decimal16]] || E0 E1 || 2 2 |
|} | |} | ||
| + | |||
| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 09:33, 9 February 2015
Double the scalar width of the elements of a decimal float vector.
Decimal floats can be 4-16 byte wide. Although the 4 byte format is a pure interchange format and no floating arithmetic operations are available for them.
Vector widen operations always produce two result vectors to accomodate the widening of maximum size vectors. The first result vector then contains the widened values of the lower half of the operand, and the second result the upper.
operands: like Widenvd DD:2D2D
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | 2 2 |
| Decimal16 | E0 E1 | 2 2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
