Difference between revisions of "Instruction Set/widens"

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(Created page with "{{DISPLAYTITLE:widens}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu block...")
 
 
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{{DISPLAYTITLE:widens}}
 
{{DISPLAYTITLE:widens}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
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widen to double width
+
Double the scalar width of a signed integer.
 +
 
 +
Sign extends the upper half.
 +
 
 +
The natively available byte widths on all [[Cores]] are 1, 2, 4, 8, and on the high end also 16.
 +
 
 +
 
 
----
 
----
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<code style="font-size:130%"><b style="color:#050">widens</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">v</span>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
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<code style="font-size:130%"><b style="color:#050">widens</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">op0</span>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and vector length (exu)">width0</span></i>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
 
</div>
 
</div>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#904|Tin]] || E0 || b:h=1 h:w=1 w:d=2 d:q=2
+
| [[Cores/Tin/Encoding#widens|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#904|Copper]] || E0 E1 || b:h=1 h:w=1 w:d=2 d:q=2
+
| [[Cores/Copper/Encoding#widens|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#904|Silver]] || E0 E1 E2 E3 || b:h=1 h:w=1 w:d=2 d:q=2
+
| [[Cores/Silver/Encoding#widens|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#904|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b:h=1 h:w=1 w:d=2 d:q=2
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| [[Cores/Gold/Encoding#widens|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#904|Decimal8]] || E0 E1 E2 E3 || b:h=1 h:w=1 w:d=2 d:q=2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#904|Decimal16]] || E0 E1 E2 E3 || b:h=1 h:w=1 w:d=2 d:q=2
+
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:14, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the signed integer value domain  

native on: all

Double the scalar width of a signed integer.

Sign extends the upper half.

The natively available byte widths on all Cores are 1, 2, 4, 8, and on the high end also 16.


widens(s op0, width width0) → s r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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