Difference between revisions of "Instruction Set/exuArgs"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:exuArgs}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bloc...")
 
 
(4 intermediate revisions by the same user not shown)
Line 1:Line 1:
 
{{DISPLAYTITLE:exuArgs}}
 
{{DISPLAYTITLE:exuArgs}}
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp;<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
−
additional slot for ganged exu operation
+
Additional arguments for [[Gang]]ed operations.
 +
 
 +
All data paths for the operands of compute operations are optimized for 2 operands. Yet some operations need more. For those operations, like [[Instruction_Set/fmaf|fmaf]] or [[Instruction_Set/inject|inject]], a primary opcode in one [[Slot]] and the `exuArgs` opcode in the next together form the full operation with all operands.
 +
 
 +
This is possible because neighboring [[Slot]]s and their [[Pipeline]]s can pass data between each other in a side path  without needing a full interconnecting data path.
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">exuArgs</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">arg</span>)</code>
 
<code style="font-size:130%"><b style="color:#050">exuArgs</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">arg</span>)</code>
Line 14:Line 19:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#64|Tin]] || E0 E1 || 0
+
| [[Cores/Tin/Encoding#exuArgs|Tin]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#64|Copper]] || E0 E1 || 0
+
| [[Cores/Copper/Encoding#exuArgs|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#64|Silver]] || E0 E1 E2 E3 || 0
+
| [[Cores/Silver/Encoding#exuArgs|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#64|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 0
+
| [[Cores/Gold/Encoding#exuArgs|Gold]] || E0 E1 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#64|Decimal8]] || E0 E1 E2 E3 || 0
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#64|Decimal16]] || E0 E1 E2 E3 || 0
+
 
|}
 
|}
  
Line 36:Line 37:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#65|Tin]] || E0 E1 || 0
+
| [[Cores/Tin/Encoding#exuArgs|Tin]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#65|Copper]] || E0 E1 || 0
+
| [[Cores/Copper/Encoding#exuArgs|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#65|Silver]] || E0 E1 E2 E3 || 0
+
| [[Cores/Silver/Encoding#exuArgs|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#65|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 0
+
| [[Cores/Gold/Encoding#exuArgs|Gold]] || E0 E1 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#65|Decimal8]] || E0 E1 E2 E3 || 0
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#65|Decimal16]] || E0 E1 E2 E3 || 0
+
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:11, 23 February 2021

speculable  exu stream  exu block  compute phase   operation  

native on: all

Additional arguments for Ganged operations.

All data paths for the operands of compute operations are optimized for 2 operands. Yet some operations need more. For those operations, like fmaf or inject, a primary opcode in one Slot and the `exuArgs` opcode in the next together form the full operation with all operands.

This is possible because neighboring Slots and their Pipelines can pass data between each other in a side path without needing a full interconnecting data path.

exuArgs(op arg)

operands: like Inv :


Core In Slots Latencies
Tin E0 E1 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 1

exuArgs(op arg0, op arg1)

operands: like Inv :


Core In Slots Latencies
Tin E0 E1 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Retrieved from "http://millcomputing.com/w/index.php?title=Instruction_Set/exuArgs&oldid=5322"