Difference between revisions of "Instruction Set/mulswv"
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(Created page with "{{DISPLAYTITLE:mulswv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exu block...") | |||
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{{DISPLAYTITLE:mulswv}} | {{DISPLAYTITLE:mulswv}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the signed integer value domain]] [[Overflow|using widening overflow behavior]] [[Condition Code|that produces condition codes]]<br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
| − | + | Signed integer multiply. Widening for a vector. | |
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">mulswv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code> | <code style="font-size:130%"><b style="color:#050">mulswv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#mulswv|Tin]] || E0 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#mulswv|Copper]] || E0 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#mulswv|Silver]] || E0 E1 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#mulswv|Gold]] || E0 E1 E2 E3 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#mulswv|Decimal8]] || E0 E1 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#mulswv|Decimal16]] || E0 E1 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
|} | |} | ||
| + | |||
| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 09:32, 9 February 2015
speculable exu stream exu block compute phase operation in the signed integer value domain using widening overflow behavior that produces condition codes
native on: all
Signed integer multiply. Widening for a vector.
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Copper | E0 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Silver | E0 E1 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Gold | E0 E1 E2 E3 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Decimal8 | E0 E1 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Decimal16 | E0 E1 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
