Difference between revisions of "Instruction Set/u2swv"
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(Created page with "{{DISPLAYTITLE:u2swv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream [[Decode|exu block]...") | |||
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{{DISPLAYTITLE:u2swv}} | {{DISPLAYTITLE:u2swv}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the logical value domain]] [[Overflow|using widening overflow behavior]] <br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
| − | + | Unsigned integer vector to signed integer vectors. Widening. | |
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">u2swv</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#op|op]] r<sub>0</sub>, [[Domains#op|op]] r<sub>1</sub></code> | <code style="font-size:130%"><b style="color:#050">u2swv</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#op|op]] r<sub>0</sub>, [[Domains#op|op]] r<sub>1</sub></code> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#u2swv|Tin]] || E0 || 2 2 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#u2swv|Copper]] || E0 E1 || 2 2 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#u2swv|Silver]] || E0 E1 E2 E3 || 2 2 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#u2swv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2 |
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#u2swv|Decimal8]] || E0 E1 E2 E3 || 2 2 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#u2swv|Decimal16]] || E0 E1 E2 E3 || 2 2 |
|} | |} | ||
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| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 09:31, 9 February 2015
speculable exu stream exu block compute phase operation in the logical value domain using widening overflow behavior
native on: all
Unsigned integer vector to signed integer vectors. Widening.
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 E1 | 2 2 |
| Silver | E0 E1 E2 E3 | 2 2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
| Decimal8 | E0 E1 E2 E3 | 2 2 |
| Decimal16 | E0 E1 E2 E3 | 2 2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
