Difference between revisions of "Instruction Set/integeredn"

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(Created page with "{{DISPLAYTITLE:integeredn}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu b...")
 
 
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{{DISPLAYTITLE:integeredn}}
 
{{DISPLAYTITLE:integeredn}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward negative infinity]]<br />
 
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
 
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
 
</div>
 
</div>
  
round to integral-valued float
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Exactly round a decimal float to an integer valued float. Rounds towards negative infinity.
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----
 
----
 
<code style="font-size:130%"><b style="color:#050">integeredn</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#d|d]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">integeredn</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#d|d]] r<sub>0</sub></code>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Decimal8/Encoding#473|Decimal8]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
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| [[Cores/Decimal8/Encoding#integeredn|Decimal8]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
 
|-
 
|-
| [[Cores/Decimal16/Encoding#473|Decimal16]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
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| [[Cores/Decimal16/Encoding#integeredn|Decimal16]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
 
|}
 
|}
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 09:31, 9 February 2015

speculable  exu stream  exu block  compute phase   operation   in the decimal floating point value domain   that produces condition codes and rounds toward negative infinity

native on: Decimal8 Decimal16

Exactly round a decimal float to an integer valued float. Rounds towards negative infinity.


integeredn(d x) → d r0

operands: like Addd [dd:d]


Core In Slots Latencies
Decimal8 E0 E1 d:d=4 dv:dv=4 q:q=5 qv:qv=5
Decimal16 E0 E1 d:d=4 dv:dv=4 q:q=5 qv:qv=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable