Difference between revisions of "Instruction Set/rd"

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(Created page with "{{DISPLAYTITLE:rd}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|reader block]...")
 
 
(3 intermediate revisions by the same user not shown)
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{{DISPLAYTITLE:rd}}
 
{{DISPLAYTITLE:rd}}
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|reader block]]&nbsp;&nbsp;[[Phasing|reader phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|reader block]]&nbsp;&nbsp;[[Phasing|reader phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
Line 14:Line 14:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#715|Tin]] || R0 R1 || 0
+
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#715|Copper]] || R0 R1 || 0
+
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#715|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#715|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#715|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#715|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
 
|}
 
|}
  
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">rd</b>(<span style="color:#009">[[Sources#scratch|scratch]]</span> <span title="scratchpad byte number">src</span>)</code>
+
<code style="font-size:130%"><b style="color:#050">rd</b>(<span style="color:#009">[[Sources#reg|reg]]</span> <span title="special register name (as used in a Reader)">src</span>)</code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoArgs|like NoArgs :[x]]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoArgs|like NoArgs :[x]]]
 
</div>
 
</div>
Line 36:Line 32:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#714|Tin]] || R0 R1 || 0
+
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#714|Copper]] || R0 R1 || 0
+
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#714|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#714|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#714|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#714|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
 
|}
 
|}
  
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">rd</b>(<span style="color:#009">[[Sources#reg|reg]]</span> <span title="special register name (as used in a Reader)">src</span>)</code>
+
<code style="font-size:130%"><b style="color:#050">rd</b>(<span style="color:#009">[[Sources#stream|stream]]</span> <span title="streamer number (as used in a Reader)">src</span>)</code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoArgs|like NoArgs :[x]]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoArgs|like NoArgs :[x]]]
 
</div>
 
</div>
Line 58:Line 50:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#712|Tin]] || R0 R1 || 0
+
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#712|Copper]] || R0 R1 || 0
+
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#712|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#712|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#712|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#712|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
 
|}
 
|}
  
−
----
 
−
<code style="font-size:130%"><b style="color:#050">rd</b>(<span style="color:#009">[[Sources#stream|stream]]</span> <span title="streamer number (as used in a Reader)">src</span>)</code>
 
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoArgs|like NoArgs :[x]]]
 
−
</div>
 
−
<br />
 
  
−
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
+
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
−
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
+
−
|-
+
−
| [[Cores/Tin/Encoding#713|Tin]] || R0 R1 || 0
+
−
|-
+
−
| [[Cores/Copper/Encoding#713|Copper]] || R0 R1 || 0
+
−
|-
+
−
| [[Cores/Silver/Encoding#713|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
−
|-
+
−
| [[Cores/Gold/Encoding#713|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
−
|-
+
−
| [[Cores/Decimal8/Encoding#713|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#713|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
−
|}
+

Latest revision as of 14:09, 23 February 2021

speculable  exu stream  reader block  reader phase   operation   in the logical value domain  

native on: all

hardware reader

rd(const src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 1
Copper R0 R1 1
Silver R0 R1 R2 R3 1
Gold R0 R1 1

rd(reg src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 1
Copper R0 R1 1
Silver R0 R1 R2 R3 1
Gold R0 R1 1

rd(stream src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 1
Copper R0 R1 1
Silver R0 R1 R2 R3 1
Gold R0 R1 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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