Difference between revisions of "Instruction Set/widensv"
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{{DISPLAYTITLE:widensv}} | {{DISPLAYTITLE:widensv}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the signed integer value domain]] <br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
| − | widen to | + | Double the scalar widths in an signed integer vector. |
| + | |||
| + | Sign extends the upper half. | ||
| + | |||
| + | The natively available byte widths on all [[Cores]] are 1, 2, 4, 8, and on the high end also 16. | ||
| + | |||
| + | Vector widen operations always produce two result vectors to accomodate the widening of maximum size vectors. The first result vector then contains the widened values of the lower half elements of the operand, and the second result the upper elements. | ||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">widensv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">v</span>) → [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code> | <code style="font-size:130%"><b style="color:#050">widensv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">v</span>) → [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#widensv|Tin]] || E0 || 2 2 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#widensv|Copper]] || E0 E1 || 2 2 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#widensv|Silver]] || E0 E1 E2 E3 || 2 2 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#widensv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2 |
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#widensv|Decimal8]] || E0 E1 E2 E3 || 2 2 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#widensv|Decimal16]] || E0 E1 E2 E3 || 2 2 |
|} | |} | ||
| + | |||
| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 09:30, 9 February 2015
speculable exu stream exu block compute phase operation in the signed integer value domain
native on: all
Double the scalar widths in an signed integer vector.
Sign extends the upper half.
The natively available byte widths on all Cores are 1, 2, 4, 8, and on the high end also 16.
Vector widen operations always produce two result vectors to accomodate the widening of maximum size vectors. The first result vector then contains the widened values of the lower half elements of the operand, and the second result the upper elements.
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 E1 | 2 2 |
| Silver | E0 E1 E2 E3 | 2 2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
| Decimal8 | E0 E1 E2 E3 | 2 2 |
| Decimal16 | E0 E1 E2 E3 | 2 2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
