Difference between revisions of "Instruction Set/innern"

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(Created page with "{{DISPLAYTITLE:innern}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow blo...")
 
 
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</div>
 
</div>
  
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enter a loop
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Enter loop that produces multiple result values.
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This is a gang encoding for loop calls that have more arguments than one slot [[Instruction_Set/inner|inner]] operations can accommodate.
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There are optimizations for this for ganged function calls with zero or one return value.
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As with all ganged inner operations, the target address is always in the last gang slot.
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<b>related operations:</b>  [[Instruction_Set/innertrn|innertrn]], [[Instruction_Set/innerfln|innerfln]]
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----
 
----
 
<code style="font-size:130%"><b style="color:#050">innern</b>(<i><span style="color:#009">[[Immediates#lit|lit]]</span> <span title="morsel-sized manifest constant">n</span></i>, <span style="color:#009">[[Domains#p|p]]</span> <span title="call argument from calls window">target</span>, <span style="color:#009">[[Domains#args|args]]</span> <span title="zero or more call  
 
<code style="font-size:130%"><b style="color:#050">innern</b>(<i><span style="color:#009">[[Immediates#lit|lit]]</span> <span title="morsel-sized manifest constant">n</span></i>, <span style="color:#009">[[Domains#p|p]]</span> <span title="call argument from calls window">target</span>, <span style="color:#009">[[Domains#args|args]]</span> <span title="zero or more call  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
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| [[Cores/Tin/Encoding#1011|Tin]] || F0 || 1
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| [[Cores/Tin/Encoding#innern|Tin]] || F0 || 1
 
|-
 
|-
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| [[Cores/Copper/Encoding#1011|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#innern|Copper]] || F0 F1 || 1
 
|-
 
|-
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| [[Cores/Silver/Encoding#1011|Silver]] || F0 F1 F2 || 1
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| [[Cores/Silver/Encoding#innern|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
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| [[Cores/Gold/Encoding#1011|Gold]] || F0 F1 F2 F3 || 1
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| [[Cores/Gold/Encoding#innern|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
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| [[Cores/Decimal8/Encoding#1011|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#innern|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
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| [[Cores/Decimal16/Encoding#1011|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#innern|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1012|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#innern|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1012|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#innern|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1012|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#innern|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1012|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#innern|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1012|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#innern|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1012|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#innern|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 17:47, 4 February 2015

realizing  flow stream  flow block  call phase   operation  

native on: all

Enter loop that produces multiple result values.

This is a gang encoding for loop calls that have more arguments than one slot inner operations can accommodate.

There are optimizations for this for ganged function calls with zero or one return value. As with all ganged inner operations, the target address is always in the last gang slot.

related operations: innertrn, innerfln

innern(lit n, p target, args args) → ops r0 ...rn

operands: like Inv :


encoding: innern(lit n, p target, off argv, count argc) , innern(lit n, p target, off argv, count argc, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

innern(lit n, lbl target, args args) → ops r0 ...rn

operands: like Inv :


encoding: innern(lit n, off target, count argc) , innern(lit n, off target, count argc, lit argv) , innern(lit n, off target, count argc, lit argv, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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