Difference between revisions of "Instruction Set/narrowux"
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| − | + | Half the width of an unsigned integer value. Exception on overflow. | |
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| + | This is not a [[Speculable]] operation. The reason for this is the impossibility to fit all of the [[NaR]] payload into values smaller than 32bit. | ||
| + | Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. | ||
| + | If narrowing should prove a big bottleneck this can be revisited. | ||
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| − | <code style="font-size:130%"><b style="color:#050">narrowux</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window"> | + | <code style="font-size:130%"><b style="color:#050">narrowux</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">op0</span>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and vector length (exu)">width0</span></i>) → [[Domains#u|u]] r<sub>0</sub></code> |
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNarrow|like Narrow [xx:½x]]] | <div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNarrow|like Narrow [xx:½x]]] | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
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| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#narrowux|Tin]] || E0 || |
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| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#narrowux|Copper]] || E0 || |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#narrowux|Silver]] || E0 E1 E2 E3 || |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#narrowux|Gold]] || E0 || |
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| − | + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | |
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Latest revision as of 14:05, 23 February 2021
realizing exu stream exu block compute phase operation in the unsigned integer value domain using excepting overflow behavior
native on: all
Half the width of an unsigned integer value. Exception on overflow.
This is not a Speculable operation. The reason for this is the impossibility to fit all of the NaR payload into values smaller than 32bit. Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. If narrowing should prove a big bottleneck this can be revisited.
narrowux(u op0, width width0) → u r0
operands: like Narrow [xx:½x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 E2 E3 | |
| Gold | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
