Difference between revisions of "Instruction Set/nope"
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(Created page with "{{DISPLAYTITLE:nope}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream exu block...") | |||
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{{DISPLAYTITLE:nope}} | {{DISPLAYTITLE:nope}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the logical value domain]] <br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
| − | + | No operation. Exu side. | |
| + | |||
| + | Usually doesn't need to be encoded, since delays are encoded in the [[Block|encoding gap]]. | ||
| + | But for the block sizes that don't have an encoding gap, which are known for each [[Core]], the leftover entropy in the instruction header for those block sizes can encode <abbr title="No Operation">NOP</abbr>s, too. | ||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">nope</b>()</code> | <code style="font-size:130%"><b style="color:#050">nope</b>()</code> | ||
| Line 15: | Line 19: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#nope|Tin]] || e0 E0 || 1 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#nope|Copper]] || e0 E0 || 1 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#nope|Silver]] || e0 E0 || 1 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#nope|Gold]] || e0 E0 || 1 |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
|} | |} | ||
| + | |||
| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 14:05, 23 February 2021
No operation. Exu side.
Usually doesn't need to be encoded, since delays are encoded in the encoding gap. But for the block sizes that don't have an encoding gap, which are known for each Core, the leftover entropy in the instruction header for those block sizes can encode NOPs, too.
nope()
operands: like NoArgs :[x]
alternate encoding: skinny
| Core | In Slots | Latencies |
|---|---|---|
| Tin | e0 E0 | 1 |
| Copper | e0 E0 | 1 |
| Silver | e0 E0 | 1 |
| Gold | e0 E0 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
