Difference between revisions of "Instruction Set/mulsfs"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:mulsfs}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exu block...") | |||
| (4 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
{{DISPLAYTITLE:mulsfs}} | {{DISPLAYTITLE:mulsfs}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the signed fixed point value domain]] [[Overflow|using saturating overflow behavior]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds use current dynamic rounding mode]]<br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
| − | + | Signed Fixed Point multiply. Uses current dynamic rounding mode. | |
| + | Saturating. | ||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">mulsfs</b>(<span style="color:#009">[[Domains#sf|sf]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#sf|sf]]</span> <span title="belt operand from ops window">y</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">dot</span></i>) → [[Domains#sf|sf]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">mulsfs</b>(<span style="color:#009">[[Domains#sf|sf]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#sf|sf]]</span> <span title="belt operand from ops window">y</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">dot</span></i>) → [[Domains#sf|sf]] r<sub>0</sub></code> | ||
| Line 14: | Line 16: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#mulsfs|Tin]] || E0 || |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#mulsfs|Copper]] || E0 || |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#mulsfs|Silver]] || E0 E1 || |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#mulsfs|Gold]] || E0 || |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
|} | |} | ||
| + | |||
| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 14:04, 23 February 2021
speculable exu stream exu block compute phase operation in the signed fixed point value domain using saturating overflow behavior that produces condition codes and rounds use current dynamic rounding mode
native on: all
Signed Fixed Point multiply. Uses current dynamic rounding mode. Saturating.
mulsfs(sf x, sf y, bit dot) → sf r0
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 | |
| Gold | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
