Difference between revisions of "Instruction Set/inner1"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:inner1}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow blo...")
 
 
(2 intermediate revisions by the same user not shown)
Line 4:Line 4:
 
</div>
 
</div>
  
−
enter a loop
+
Enter loop that produces one result value.
 +
 
 +
An optimization for the common case of loops with one result value. There are only gang encodings of this, for loops with more arguments than the one slot [[Instruction_Set/inner|inner]] operations can accomodate.
 +
 
 +
As with all ganged inner operations, the target address is always in the last gang slot.
 +
 
 +
<b>related operations:</b>  [[Instruction_Set/innertr1|innertr1]], [[Instruction_Set/innerfl1|innerfl1]]
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">inner1</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="call argument from calls window">target</span>, <span style="color:#009">[[Domains#args|args]]</span> <span title="zero or more call arguments from calls window">args</span>) &#8594; [[Domains|op]] r</code>
 
<code style="font-size:130%"><b style="color:#050">inner1</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="call argument from calls window">target</span>, <span style="color:#009">[[Domains#args|args]]</span> <span title="zero or more call arguments from calls window">args</span>) &#8594; [[Domains|op]] r</code>
Line 25:Line 32:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1003|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#inner1|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1003|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#inner1|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1003|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#inner1|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1003|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#inner1|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1003|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#inner1|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1003|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#inner1|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
Line 60:Line 67:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1004|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#inner1|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1004|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#inner1|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1004|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#inner1|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1004|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#inner1|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1004|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#inner1|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1004|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#inner1|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 17:45, 4 February 2015

realizing  flow stream  flow block  call phase   operation  

native on: all

Enter loop that produces one result value.

An optimization for the common case of loops with one result value. There are only gang encodings of this, for loops with more arguments than the one slot inner operations can accomodate.

As with all ganged inner operations, the target address is always in the last gang slot.

related operations: innertr1, innerfl1

inner1(p target, args args) → op r

operands: like Inv :


encoding: inner1(op q, off target, count argc) , inner1(op q, off target, count argc, lit argv) , inner1(op q, off target, count argc, lit argv, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

inner1(lbl target, args args) → op r

operands: like Inv :


encoding: inner1(off target, count argc) , inner1(off target, count argc, lit argv) , inner1(off target, count argc, lit argv, lit argv) , inner1(off target, count argc, lit argv, lit argv, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Retrieved from "http://millcomputing.com/w/index.php?title=Instruction_Set/inner1&oldid=3556"