Difference between revisions of "Instruction Set/rotate"

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(Created page with "{{DISPLAYTITLE:rotate}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|reader bl...")
 
 
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{{DISPLAYTITLE:rotate}}
 
{{DISPLAYTITLE:rotate}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|reader block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|reader block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#745|Tin]] || R0 R1 || 1
+
| [[Cores/Tin/Encoding#rotate|Tin]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#745|Copper]] || R0 R1 || 1
+
| [[Cores/Copper/Encoding#rotate|Copper]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#745|Silver]] || R0 R1 R2 R3 R4 R5 || 1
+
| [[Cores/Silver/Encoding#rotate|Silver]] || R0 R1 R2 R3 R4 R5 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#745|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 1
+
| [[Cores/Gold/Encoding#rotate|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#745|Decimal8]] || R0 R1 R2 R3 R4 R5 || 1
+
| [[Cores/Decimal8/Encoding#rotate|Decimal8]] || R0 R1 R2 R3 R4 R5 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#745|Decimal16]] || R0 R1 R2 R3 R4 R5 || 1
+
| [[Cores/Decimal16/Encoding#rotate|Decimal16]] || R0 R1 R2 R3 R4 R5 || 1
 
|}
 
|}
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 +
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 09:29, 9 February 2015

speculable  exu stream  reader block  compute phase   operation   in the logical value domain  

native on: all

bitwise rotate

rotate(scratch id)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 1
Copper R0 R1 1
Silver R0 R1 R2 R3 R4 R5 1
Gold R0 R1 R2 R3 R4 R5 R6 R7 1
Decimal8 R0 R1 R2 R3 R4 R5 1
Decimal16 R0 R1 R2 R3 R4 R5 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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