Difference between revisions of "Instruction Set/addffz"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:addffz}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu block...")
 
 
(5 intermediate revisions by the same user not shown)
Line 1:Line 1:
 
{{DISPLAYTITLE:addffz}}
 
{{DISPLAYTITLE:addffz}}
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds to nearest, ties away from zero]]<br />
−
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
+
'''native on:''' [[Cores/Silver|Silver]] <br />
 
</div>
 
</div>
  
−
addition
+
Floating point add in current rounding away from zero.
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">addffz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">addffz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
Line 14:Line 15:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#188|Silver]] || E0 E1 || w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
+
| [[Cores/Silver/Encoding#addffz|Silver]] || E0 E1 ||  
−
|-
+
−
| [[Cores/Gold/Encoding#188|Gold]] || E0 E1 E2 E3 || w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
+
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:02, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the binary floating point value domain   that produces condition codes and rounds to nearest, ties away from zero

native on: Silver

Floating point add in current rounding away from zero.

addffz(f x, f y) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Retrieved from "http://millcomputing.com/w/index.php?title=Instruction_Set/addffz&oldid=4779"