Difference between revisions of "Instruction Set/divfz"
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(Created page with "{{DISPLAYTITLE:divfz}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream [[Decode|exu block]...") | |||
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{{DISPLAYTITLE:divfz}} | {{DISPLAYTITLE:divfz}} | ||
− | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward zero]]<br /> |
− | '''native on:''' [[ | + | '''native on:''' [[Cores/Silver|Silver]] <br /> |
</div> | </div> | ||
− | + | Floating point division in current rounding towards zero. | |
+ | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">divfz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#f|f]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">divfz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#f|f]] r<sub>0</sub></code> | ||
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</div> | </div> | ||
<br /> | <br /> | ||
+ | |||
+ | {| class="mw-collapsible mw-collapsed wikitable" data-expandtext="▸" data-collapsetext="▾" | ||
+ | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
+ | |- | ||
+ | | [[Cores/Silver/Encoding#divfz|Silver]] || E0 || | ||
+ | |} | ||
+ | |||
+ | |||
+ | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] |
Latest revision as of 14:00, 23 February 2021
speculable exu stream exu block compute phase operation in the binary floating point value domain that produces condition codes and rounds toward zero
native on: Silver
Floating point division in current rounding towards zero.
operands: like Addf [ff:f]
Core | In Slots | Latencies |
---|---|---|
Silver | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable