Difference between revisions of "Instruction Set/retntr"
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| − | + | Conditionally returns values and control to the caller on true. | |
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| + | Returns count as branches, which means with coniditional returns the [[First Winner Rule]] applies. | ||
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| + | <b>related operations:</b> [[Instruction_Set/retn]] | ||
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---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">retntr</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">q</span>, <span style="color:#009">[[Domains#ops|ops]]</span> <span title="one or more return arguments">vs</span>) → [[Domains|ops]] r<sub>0</sub> ...</code> | <code style="font-size:130%"><b style="color:#050">retntr</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">q</span>, <span style="color:#009">[[Domains#ops|ops]]</span> <span title="one or more return arguments">vs</span>) → [[Domains|ops]] r<sub>0</sub> ...</code> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#retntr|Tin]] || F0 || 1 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#retntr|Copper]] || F0 || 1 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#retntr|Silver]] || F0 F1 F2 || 1 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#retntr|Gold]] || F0 || 1 |
| − | + | ||
| − | + | ||
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|} | |} | ||
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| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 14:01, 23 February 2021
Conditionally returns values and control to the caller on true.
Returns count as branches, which means with coniditional returns the First Winner Rule applies.
related operations: Instruction_Set/retn
retntr(pred q, ops vs) → ops r0 ...
operands: like Inv :
encoding:
retntr(pred q, off vs, count c)
,
retntr(pred q, off vs, count c, lit vs)
,
retntr(pred q, off vs, count c, lit vs, lit vs)
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 | 1 |
| Silver | F0 F1 F2 | 1 |
| Gold | F0 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
