Difference between revisions of "Instruction Set/divu"
From Mill Computing Wiki
| Line 17: | Line 17: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Silver/Encoding#divu|Silver]] || E0 || | + | | [[Cores/Silver/Encoding#divu|Silver]] || E0 || |
|} | |} | ||
| Line 29: | Line 29: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Silver/Encoding#divu|Silver]] || E0 || | + | | [[Cores/Silver/Encoding#divu|Silver]] || E0 || |
|} | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 14:09, 23 February 2021
speculable exu stream exu block compute phase operation in the unsigned integer value domain that produces condition codes
native on: Silver
Unsigned integer division for quotient.
related operations: remu, divRemu, rdivu, rootu, rrootu
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 |
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
