Difference between revisions of "Instruction Set/divRemu"
From Mill Computing Wiki
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
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| − | | [[Cores/Silver/Encoding#divRemu|Silver]] || E0 || | + | | [[Cores/Silver/Encoding#divRemu|Silver]] || E0 || |
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Silver/Encoding#divRemu|Silver]] || E0 || | + | | [[Cores/Silver/Encoding#divRemu|Silver]] || E0 || |
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 14:04, 23 February 2021
speculable exu stream exu block compute phase operation in the unsigned integer value domain that produces condition codes
native on: Silver
Unsigned integer division for quotient and remainder.
related operations: divu, remu, rdivu, rootu, rrootu
divRemu(u x, u y) → u r0, u r1
operands: like DivRem [xx:xx]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 |
divRemu(u x, imm y) → u r0, u r1
operands: like DivRem [xx:xx]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
