Difference between revisions of "Instruction Set/exuArgs"

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Line 19:Line 19:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#exuArgs|Tin]] || E0 E1 || 0
+
| [[Cores/Tin/Encoding#exuArgs|Tin]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#exuArgs|Copper]] || E0 E1 || 0
+
| [[Cores/Copper/Encoding#exuArgs|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#exuArgs|Silver]] || E0 E1 E2 E3 || 0
+
| [[Cores/Silver/Encoding#exuArgs|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#exuArgs|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 0
+
| [[Cores/Gold/Encoding#exuArgs|Gold]] || E0 E1 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#exuArgs|Decimal8]] || E0 E1 E2 E3 || 0
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#exuArgs|Decimal16]] || E0 E1 E2 E3 || 0
+
 
|}
 
|}
  
Line 41:Line 37:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#exuArgs|Tin]] || E0 E1 || 0
+
| [[Cores/Tin/Encoding#exuArgs|Tin]] || E0 E1 || 1
−
|-
+
−
| [[Cores/Copper/Encoding#exuArgs|Copper]] || E0 E1 || 0
+
−
|-
+
−
| [[Cores/Silver/Encoding#exuArgs|Silver]] || E0 E1 E2 E3 || 0
+
 
|-
 
|-
−
| [[Cores/Gold/Encoding#exuArgs|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 0
+
| [[Cores/Copper/Encoding#exuArgs|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#exuArgs|Decimal8]] || E0 E1 E2 E3 || 0
+
| [[Cores/Silver/Encoding#exuArgs|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#exuArgs|Decimal16]] || E0 E1 E2 E3 || 0
+
| [[Cores/Gold/Encoding#exuArgs|Gold]] || E0 E1 || 1
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:11, 23 February 2021

speculable  exu stream  exu block  compute phase   operation  

native on: all

Additional arguments for Ganged operations.

All data paths for the operands of compute operations are optimized for 2 operands. Yet some operations need more. For those operations, like fmaf or inject, a primary opcode in one Slot and the `exuArgs` opcode in the next together form the full operation with all operands.

This is possible because neighboring Slots and their Pipelines can pass data between each other in a side path without needing a full interconnecting data path.

exuArgs(op arg)

operands: like Inv :


Core In Slots Latencies
Tin E0 E1 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 1

exuArgs(op arg0, op arg1)

operands: like Inv :


Core In Slots Latencies
Tin E0 E1 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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