Difference between revisions of "Instruction Set/f2ude"

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{{DISPLAYTITLE:f2ude}}
 
{{DISPLAYTITLE:f2ude}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp; [[Overflow|using modulo overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds to nearest, ties toward even adjacent value]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp; [[Overflow|using modulo overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds use current dynamic rounding mode]]<br />
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'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
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'''native on:''' [[Assembly|none]]<br />
 
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<code style="font-size:130%"><b style="color:#050">f2ude</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#d|d]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">f2ude</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#d|d]] r<sub>0</sub></code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeAddd|like Addd [dd:d]]]
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeAddf|like Addf [ff:f]]]
 
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{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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|-
 
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| [[Cores/Decimal8/Encoding#f2ude|Decimal8]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5
 
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|-
 
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| [[Cores/Decimal16/Encoding#f2ude|Decimal16]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5
 
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|}
 
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:05, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the decimal floating point value domain   using modulo overflow behavior   that produces condition codes and rounds use current dynamic rounding mode

native on: none

Inexactly convert a decimal floating point value to a unsigned integer, rounding toward even and normal modulo overflow.

f2ude(d x) → d r0

operands: like Addf [ff:f]



Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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