Difference between revisions of "Instruction Set/widenf"

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{{DISPLAYTITLE:widenf}}
 
{{DISPLAYTITLE:widenf}}
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp;<br />
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp;<br />
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
+
'''native on:''' [[Cores/Silver|Silver]] <br />
 
</div>
 
</div>
  
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----
 
----
<code style="font-size:130%"><b style="color:#050">widenf</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">v</span>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
+
<code style="font-size:130%"><b style="color:#050">widenf</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">op0</span>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and vector length (exu)">width0</span></i>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWidenf|like Widenf ff:2f]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWidenf|like Widenf ff:2f]]
 
</div>
 
</div>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Silver/Encoding#widenf|Silver]] || E0 E1 || 1
+
| [[Cores/Silver/Encoding#widenf|Silver]] || E0 E1 ||  
|-
+
| [[Cores/Gold/Encoding#widenf|Gold]] || E0 E1 E2 E3 || 1
+
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:04, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the binary floating point value domain  

native on: Silver

Double the scalar width of a binary float.

Binary floats can be 2-16 byte wide. Although the 2 byte format is a pure interchange format and no floating arithmetic operations are available for them.



widenf(f op0, width width0) → f r0

operands: like Widenf ff:2f


Core In Slots Latencies
Silver E0 E1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable