Difference between revisions of "Instruction Set/mulufwp"
From Mill Computing Wiki
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding#mulufwp|Tin]] || E0 || | + | | [[Cores/Tin/Encoding#mulufwp|Tin]] || E0 || |
|- | |- | ||
− | | [[Cores/Copper/Encoding#mulufwp|Copper]] || E0 || | + | | [[Cores/Copper/Encoding#mulufwp|Copper]] || E0 || |
|- | |- | ||
− | | [[Cores/Silver/Encoding#mulufwp|Silver]] || E0 E1 || | + | | [[Cores/Silver/Encoding#mulufwp|Silver]] || E0 E1 || |
|- | |- | ||
− | | [[Cores/Gold/Encoding#mulufwp|Gold]] || E0 | + | | [[Cores/Gold/Encoding#mulufwp|Gold]] || E0 || |
− | + | ||
− | + | ||
− | + | ||
− | + | ||
|} | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] |
Latest revision as of 13:26, 23 February 2021
speculable exu stream exu block compute phase operation in the unsigned fixed point value domain using widening overflow behavior that produces condition codes and rounds toward positive infinity
native on: all
Unsigned Fixed Point multiply. Rounds towards positive infinity. Widening.
mulufwp(uf x, uf y, bit dot) → uf r0
operands: like Identity [xx:x]
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | |
Copper | E0 | |
Silver | E0 E1 | |
Gold | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable