Difference between revisions of "Instruction Set/alternate"
From Mill Computing Wiki
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding#alternate|Tin]] || E0 || | + | | [[Cores/Tin/Encoding#alternate|Tin]] || E0 || |
|- | |- | ||
− | | [[Cores/Copper/Encoding#alternate|Copper]] || E0 | + | | [[Cores/Copper/Encoding#alternate|Copper]] || E0 || |
|- | |- | ||
− | | [[Cores/Silver/Encoding#alternate|Silver]] || E0 E1 E2 E3 || | + | | [[Cores/Silver/Encoding#alternate|Silver]] || E0 E1 E2 E3 || |
|- | |- | ||
− | | [[Cores/Gold/Encoding#alternate|Gold]] || E0 | + | | [[Cores/Gold/Encoding#alternate|Gold]] || E0 || |
− | + | ||
− | + | ||
− | + | ||
− | + | ||
|} | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] |
Latest revision as of 13:57, 23 February 2021
Interlace two Vectors. i.e. take two vectors [a b c d] and [1 2 3 4] and produce two vectors [a 1 b 2] and [c 3 d 4]. The actual number of vector elements is dependent on the scalar domain width and the vector operand width of the specific core.
related operations: shuffle, vec, inject, extract
alternate(op v1, op v2) → op r0, op r1
operands: like Alternate XX:XX
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | |
Copper | E0 | |
Silver | E0 E1 E2 E3 | |
Gold | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable