Difference between revisions of "Instruction Set/divu"

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{{DISPLAYTITLE:divu}}
 
{{DISPLAYTITLE:divu}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
'''native on:''' [[Assembly|none]]<br />
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'''native on:''' [[Cores/Silver|Silver]] <br />
 
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{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
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|-
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| [[Cores/Silver/Encoding#divu|Silver]] || E0 ||
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|}
  
 
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{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
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|-
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| [[Cores/Silver/Encoding#divu|Silver]] || E0 ||
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|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:09, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   that produces condition codes

native on: Silver

Unsigned integer division for quotient.

related operations: remu, divRemu, rdivu, rootu, rrootu


divu(u x, u y) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Silver E0

divu(u x, imm y) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Silver E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable