Difference between revisions of "Instruction Set/widensf"

From Mill Computing Wiki
Jump to: navigation, search
 
(One intermediate revision by the same user not shown)
Line 1:Line 1:
 
{{DISPLAYTITLE:widensf}}
 
{{DISPLAYTITLE:widensf}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed fixed point value domain]]&nbsp;&nbsp;<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed fixed point value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
Line 11:Line 11:
  
 
----
 
----
<code style="font-size:130%"><b style="color:#050">widensf</b>(<span style="color:#009">[[Domains#sf|sf]]</span> <span title="belt operand from ops window">v</span>) &#8594; [[Domains#sf|sf]] r<sub>0</sub></code>
+
<code style="font-size:130%"><b style="color:#050">widensf</b>(<span style="color:#009">[[Domains#sf|sf]]</span> <span title="belt operand from ops window">op0</span>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and vector length (exu)">width0</span></i>) &#8594; [[Domains#sf|sf]] r<sub>0</sub></code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
 
</div>
 
</div>
Line 19:Line 19:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#widensf|Tin]] || E0 || b:h=1 h:w=1 w:d=1 d:q=2
+
| [[Cores/Tin/Encoding#widensf|Tin]] || E0 ||  
 
|-
 
|-
| [[Cores/Copper/Encoding#widensf|Copper]] || E0 E1 || b:h=1 h:w=1 w:d=1 d:q=2
+
| [[Cores/Copper/Encoding#widensf|Copper]] || E0 ||  
 
|-
 
|-
| [[Cores/Silver/Encoding#widensf|Silver]] || E0 E1 E2 E3 || b:h=1 h:w=1 w:d=1 d:q=2
+
| [[Cores/Silver/Encoding#widensf|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
| [[Cores/Gold/Encoding#widensf|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b:h=1 h:w=1 w:d=1 d:q=2
+
| [[Cores/Gold/Encoding#widensf|Gold]] || E0 ||  
|-
+
| [[Cores/Decimal8/Encoding#widensf|Decimal8]] || E0 E1 E2 E3 || b:h=1 h:w=1 w:d=1 d:q=2
+
|-
+
| [[Cores/Decimal16/Encoding#widensf|Decimal16]] || E0 E1 E2 E3 || b:h=1 h:w=1 w:d=1 d:q=2
+
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:10, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the signed fixed point value domain  

native on: all

Double the scalar width of a signed fixed point value.

The reason a special widen for fixed point is needed is because the fixed point is defined relative to the most significant side. Widening increases precision, but doesn't extend the value range.

The natively available byte widths on all Cores are 1, 2, 4, 8, and on the high end also 16.


widensf(sf op0, width width0) → sf r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable