Difference between revisions of "Instruction Set/shiftlswv"
From Mill Computing Wiki
| Line 1: | Line 1: | ||
{{DISPLAYTITLE:shiftlswv}} | {{DISPLAYTITLE:shiftlswv}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the signed integer value domain]] [[Overflow|using widening overflow behavior]] [[Condition Code|that produces condition codes]]<br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
Latest revision as of 09:24, 9 February 2015
speculable exu stream exu block compute phase operation in the signed integer value domain using widening overflow behavior that produces condition codes
native on: all
Signed bitwise vector left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get sign extended in the widening. Produces two result vectors.
shiftlswv(s x, bit bits) → s r0, s r1
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 | 2 2 |
| Silver | E0 E1 | 2 2 |
| Gold | E0 E1 | 2 2 |
| Decimal8 | E0 E1 | 2 2 |
| Decimal16 | E0 E1 | 2 2 |
shiftlswv(s x, n bits) → s r0, s r1
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 | 2 2 |
| Silver | E0 E1 | 2 2 |
| Gold | E0 E1 | 2 2 |
| Decimal8 | E0 E1 | 2 2 |
| Decimal16 | E0 E1 | 2 2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
