Difference between revisions of "Instruction Set/brfl"

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</div>
 
</div>
  
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branch
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Branch on false predicate.
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----
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There can be several conditionless branches in an [[EBB]] and even in the same operation, which are all processed in parallel, but the first successful in the lowest slot wins.
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<code style="font-size:130%"><b style="color:#050">brfl</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">q</span>, <span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from opsWindow">target</span>)</code>
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−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeInv|like Inv :]]
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</div>
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<br />
+
  
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{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
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The targets in branches, whether literal or from a belt operand, are always relative to the  [[Registers|EBB entry point]]. The optional delay serves to synchronize with operations that need to finish before control is transferred to the next EBB. This is particularly important for the predicates to examine for the branch, the value of which is examined after the delay.
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
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−
|-
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The branch not taken case is more efficient and faster, i.e. the compiler takes care to schedule the conditional branches with their more likely case not to be taken, to achieve the longest possible code sequences without control transfers.
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| [[Cores/Tin/Encoding#222|Tin]] || F0 || 1
+
 
−
|-
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<b>related operations:</b> [[Instruction_Set/br|br]], [[Instruction_Set/brtr|brtr]]
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| [[Cores/Copper/Encoding#222|Copper]] || F0 F1 || 1
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−
|-
+
−
| [[Cores/Silver/Encoding#222|Silver]] || F0 F1 F2 || 1
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−
|-
+
−
| [[Cores/Gold/Encoding#222|Gold]] || F0 F1 F2 F3 || 1
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−
|-
+
−
| [[Cores/Decimal8/Encoding#222|Decimal8]] || F0 F1 F2 || 1
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−
|-
+
−
| [[Cores/Decimal16/Encoding#222|Decimal16]] || F0 F1 F2 || 1
+
−
|}
+
  
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">brfl</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">q</span>, <span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from opsWindow">target</span>, <i><span style="color:#009">[[Immediates#lit|lit]]</span> <span title="morsel-sized
+
<code style="font-size:130%"><b style="color:#050">brfl</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">op0</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from opsWindow">op1</span>, <span style="color:#009">[[Domains#ops|ops]]</span> <span title="one or more
−
             manifest constant">delay</span></i>)</code>
+
             return arguments">args</span>)</code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeInv|like Inv :]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeInv|like Inv :]]
 
</div>
 
</div>
 +
<br />
 +
 +
'''encoding:'''
 +
<code style="font-size:100%"><b style="color:#050">brfl</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">count0</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from opsWindow">op0</span>, <i><span style="color:#009">[[Immediates#off|off]]</span> <span title="manifest
 +
            constant">op1</span></i>, <i><span style="color:#009">[[Immediates#count|count]]</span> <span title="morsel-sized count of polyadic args">off0</span></i>)</code>
 +
,
 +
<code style="font-size:100%"><b style="color:#050">brfl</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">count0</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from opsWindow">op0</span>, <i><span style="color:#009">[[Immediates#off|off]]</span> <span title="manifest
 +
            constant">op1</span></i>, <i><span style="color:#009">[[Immediates#count|count]]</span> <span title="morsel-sized count of polyadic args">lit0</span></i>, <i><span style="color:#009">[[Immediates#lit|lit]]</span> <span title="morsel-sized manifest constant">off0</span></i>)</code>
 
<br />
 
<br />
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#223|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#brfl|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#223|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#brfl|Copper]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#223|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#brfl|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#223|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#brfl|Gold]] || F0 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#223|Decimal8]] || F0 F1 F2 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#223|Decimal16]] || F0 F1 F2 || 1
+
 
|}
 
|}
  
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">brfl</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">q</span>, <i><span style="color:#009">[[Immediates#lbl|lbl]]</span> <span title="name of label or function">target</span></i>)</code>
+
<code style="font-size:130%"><b style="color:#050">brfl</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">op0</span>, <i><span style="color:#009">[[Immediates#lbl|lbl]]</span> <span title="name of label or function">off0</span></i>, <span style="color:#009">[[Domains#ops|ops]]</span> <span title="one or more
 +
            return arguments">args</span>)</code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeInv|like Inv :]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeInv|like Inv :]]
 
</div>
 
</div>
 +
<br />
 +
 +
'''encoding:'''
 +
<code style="font-size:100%"><b style="color:#050">brfl</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">count0</span>, <i><span style="color:#009">[[Immediates#off|off]]</span> <span title="manifest constant">op0</span></i>, <i><span style="color:#009">[[Immediates#count|count]]</span> <span title="morsel-sized count of
 +
            polyadic args">off0</span></i>)</code>
 +
,
 +
<code style="font-size:100%"><b style="color:#050">brfl</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">count0</span>, <i><span style="color:#009">[[Immediates#off|off]]</span> <span title="manifest constant">op0</span></i>, <i><span style="color:#009">[[Immediates#count|count]]</span> <span title="morsel-sized count of
 +
            polyadic args">lit0</span></i>, <i><span style="color:#009">[[Immediates#lit|lit]]</span> <span title="morsel-sized manifest constant">off0</span></i>)</code>
 +
,
 +
<code style="font-size:100%"><b style="color:#050">brfl</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">count0</span>, <i><span style="color:#009">[[Immediates#off|off]]</span> <span title="manifest constant">op0</span></i>, <i><span style="color:#009">[[Immediates#count|count]]</span> <span title="morsel-sized count of
 +
            polyadic args">lit0</span></i>, <i><span style="color:#009">[[Immediates#lit|lit]]</span> <span title="morsel-sized manifest constant">lit1</span></i>, <i><span style="color:#009">[[Immediates#lit|lit]]</span> <span title="morsel-sized manifest constant">off0</span></i>)</code>
 
<br />
 
<br />
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#224|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#brfl|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#224|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#brfl|Copper]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#224|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#brfl|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#224|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#brfl|Gold]] || F0 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#224|Decimal8]] || F0 F1 F2 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#224|Decimal16]] || F0 F1 F2 || 1
+
 
|}
 
|}
  
−
----
 
−
<code style="font-size:130%"><b style="color:#050">brfl</b>(<span style="color:#009">[[Domains#pred|pred]]</span> <span title="late-evaluated 1-bit predicate from belt">q</span>, <i><span style="color:#009">[[Immediates#lbl|lbl]]</span> <span title="name of label or function">target</span></i>, <i><span style="color:#009">[[Immediates#lit|lit]]</span> <span title="morsel-sized
 
−
            manifest constant">delay</span></i>)</code>
 
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeInv|like Inv :]]
 
−
</div>
 
−
<br />
 
  
−
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
+
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
−
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
+
−
|-
+
−
| [[Cores/Tin/Encoding#221|Tin]] || F0 || 1
+
−
|-
+
−
| [[Cores/Copper/Encoding#221|Copper]] || F0 F1 || 1
+
−
|-
+
−
| [[Cores/Silver/Encoding#221|Silver]] || F0 F1 F2 || 1
+
−
|-
+
−
| [[Cores/Gold/Encoding#221|Gold]] || F0 F1 F2 F3 || 1
+
−
|-
+
−
| [[Cores/Decimal8/Encoding#221|Decimal8]] || F0 F1 F2 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#221|Decimal16]] || F0 F1 F2 || 1
+
−
|}
+

Latest revision as of 13:24, 23 February 2021

realizing  flow stream  flow block  transfer phase   operation  

native on: all

Branch on false predicate. There can be several conditionless branches in an EBB and even in the same operation, which are all processed in parallel, but the first successful in the lowest slot wins.

The targets in branches, whether literal or from a belt operand, are always relative to the EBB entry point. The optional delay serves to synchronize with operations that need to finish before control is transferred to the next EBB. This is particularly important for the predicates to examine for the branch, the value of which is examined after the delay.

The branch not taken case is more efficient and faster, i.e. the compiler takes care to schedule the conditional branches with their more likely case not to be taken, to achieve the longest possible code sequences without control transfers.

related operations: br, brtr

brfl(pred op0, op op1, ops args)

operands: like Inv :


encoding: brfl(pred count0, op op0, off op1, count off0) , brfl(pred count0, op op0, off op1, count lit0, lit off0)

Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 F1 F2 1
Gold F0 1

brfl(pred op0, lbl off0, ops args)

operands: like Inv :


encoding: brfl(pred count0, off op0, count off0) , brfl(pred count0, off op0, count lit0, lit off0) , brfl(pred count0, off op0, count lit0, lit lit1, lit off0)

Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 F1 F2 1
Gold F0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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