Difference between revisions of "Instruction Set/comp"

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(Created page with "{{DISPLAYTITLE:comp}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream  exu block...")
 
m (Protected "Instruction Set/comp": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
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</div>
 
</div>
  
bitwise (ones) complement
+
Bitwise ones complement.
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">comp</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">comp</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#242|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#comp|Tin]] || E0 || 1
 
|-
 
|-
| [[Cores/Copper/Encoding#242|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#comp|Copper]] || E0 E1 || 1
 
|-
 
|-
| [[Cores/Silver/Encoding#242|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#comp|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
| [[Cores/Gold/Encoding#242|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#comp|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
| [[Cores/Decimal8/Encoding#242|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#comp|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
| [[Cores/Decimal16/Encoding#242|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#comp|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 01:27, 3 January 2015

realizing  exu stream  exu block  compute phase   operation   in the logical value domain   that produces condition codes

native on: all

Bitwise ones complement.


comp(op x) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable