Difference between revisions of "Instruction Set/rrootf"

Latest revision as of 14:11, 23 February 2021

native on: Silver

Binary float reciprocal square root. i.e. the result is 1/√x.

This operation doesn't need rounding since no precision is lost.

rrootf(f x) → f r₀

operands: like Addf [ff:f]

Core	In Slots	Latencies
Silver	E0 E1	rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5

@@ Line 1: / Line 1: @@
 {{DISPLAYTITLE:rrootf}}
-<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp;<br />
+<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds use current dynamic rounding mode]]<br />
-'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
+'''native on:''' [[Cores/Silver|Silver]] <br />
 </div>
@@ Line 18: / Line 18: @@
 ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 |-
-| [[Cores/Silver/Encoding#rrootf|Silver]] || E0 E1 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5
+| [[Cores/Silver/Encoding#rrootf|Silver]] || E0 E1 || rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5
-|-
-| [[Cores/Gold/Encoding#rrootf|Gold]] || E0 E1 E2 E3 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5
 |}
 [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]