Difference between revisions of "Instruction Set/neqfx"

Latest revision as of 14:09, 23 February 2021

native on: Silver

Binary float inequality comparison. NaN-Aware. When one or both of the operands are a NaN, the comparison is false.

related operations: neqf

neqfx(f x, f y) → f r₀

Core	In Slots	Latencies
Silver	E0 E1

@@ Line 1: / Line 1: @@
 {{DISPLAYTITLE:neqfx}}
-<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp;<br />
+<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp;<br />
-'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
+'''native on:''' [[Cores/Silver|Silver]] <br />
 </div>
@@ Line 18: / Line 18: @@
 ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 |-
-| [[Cores/Silver/Encoding#neqfx|Silver]] || E0 E1 || w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
+| [[Cores/Silver/Encoding#neqfx|Silver]] || E0 E1 ||
-|-
-| [[Cores/Gold/Encoding#neqfx|Gold]] || E0 E1 E2 E3 || w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
 |}
 [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]