Difference between revisions of "Instruction Set/rd"

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m (Protected "Instruction Set/rd": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
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{{DISPLAYTITLE:rd}}
 
{{DISPLAYTITLE:rd}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|reader block]]&nbsp;&nbsp;[[Phasing|reader phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|reader block]]&nbsp;&nbsp;[[Phasing|reader phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 0
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| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 0
+
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#rd|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#rd|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
−
|}
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−
 
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----
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<code style="font-size:130%"><b style="color:#050">rd</b>(<span style="color:#009">[[Sources#scratch|scratch]]</span> <span title="scratchpad byte number">src</span>)</code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoArgs|like NoArgs :[x]]]
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</div>
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<br />
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{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
+
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
+
−
|-
+
−
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 0
+
−
|-
+
−
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 0
+
−
|-
+
−
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
−
|-
+
−
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
−
|-
+
−
| [[Cores/Decimal8/Encoding#rd|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#rd|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 0
+
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 0
+
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#rd|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#rd|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 0
+
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 1
−
|-
+
−
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 0
+
−
|-
+
−
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
 
|-
 
|-
−
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#rd|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#rd|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 || 1
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:09, 23 February 2021

speculable  exu stream  reader block  reader phase   operation   in the logical value domain  

native on: all

hardware reader

rd(const src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 1
Copper R0 R1 1
Silver R0 R1 R2 R3 1
Gold R0 R1 1

rd(reg src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 1
Copper R0 R1 1
Silver R0 R1 R2 R3 1
Gold R0 R1 1

rd(stream src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 1
Copper R0 R1 1
Silver R0 R1 R2 R3 1
Gold R0 R1 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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